c

tensil.tcu

InnerSystolicArray

class InnerSystolicArray[T <: Data with Num[T]] extends Module

Linear Supertypes
LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. InnerSystolicArray
  2. LegacyModule
  3. MultiIOModule
  4. RawModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new InnerSystolicArray(gen: T, height: Int, width: Int)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. val bias: IndexedSeq[T]
  11. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  12. final val clock: Clock
    Definition Classes
    MultiIOModule
  13. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  14. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  15. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  16. def desiredName: String
    Definition Classes
    BaseModule
  17. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  18. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  19. val gen: T
  20. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  21. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  22. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  23. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  24. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  25. def hasSeed: Boolean
    Definition Classes
    HasId
  26. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  27. val height: Int
  28. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  29. val io: Bundle { ... /* 4 definitions in type refinement */ }
    Definition Classes
    InnerSystolicArray → LegacyModule
  30. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  31. val mac: IndexedSeq[IndexedSeq[MAC[T]]]
  32. final lazy val name: String
    Definition Classes
    BaseModule
  33. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  34. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  35. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  36. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  37. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  38. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  39. def parentModName: String
    Definition Classes
    HasId → InstanceId
  40. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  41. def pathName: String
    Definition Classes
    HasId → InstanceId
  42. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  43. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  44. final val reset: Reset
    Definition Classes
    MultiIOModule
  45. def suggestName(seed: ⇒ String): InnerSystolicArray.this.type
    Definition Classes
    HasId
  46. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  47. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  48. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  49. def toString(): String
    Definition Classes
    AnyRef → Any
  50. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  51. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  52. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  53. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  54. val width: Int

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped