class TCU[T <: Data with Num[T]] extends Module

Linear Supertypes
LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
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Inherited
  1. TCU
  2. LegacyModule
  3. MultiIOModule
  4. RawModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new TCU(gen: T, layout: InstructionLayout, options: TCUOptions = TCUOptions())(implicit platformConfig: PlatformConfig)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  9. val acc: AccumulatorWithALUArray[T]
  10. val accDepth: Long
  11. val array: SystolicArray[T]
  12. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  13. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  14. final val clock: Clock
    Definition Classes
    MultiIOModule
  15. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  16. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  17. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  18. val dataPort: Port[Vec[T]]
  19. val decoder: Decoder
  20. def desiredName: String
    Definition Classes
    BaseModule
  21. val dram0Depth: Long
  22. val dram1Depth: Long
  23. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  24. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  25. val gen: T
  26. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  27. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  28. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  29. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  30. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  31. def hasSeed: Boolean
    Definition Classes
    HasId
  32. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  33. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  34. val instructionWidth: Int
  35. val io: Bundle { ... /* 10 definitions in type refinement */ }
    Definition Classes
    TCU → LegacyModule
  36. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  37. val layout: InstructionLayout
  38. val localDepth: Long
  39. val mem: DualPortMem[Vec[T]]
  40. final lazy val name: String
    Definition Classes
    BaseModule
  41. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  42. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  43. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  44. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  45. val options: TCUOptions
  46. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  47. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  48. def parentModName: String
    Definition Classes
    HasId → InstanceId
  49. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  50. def pathName: String
    Definition Classes
    HasId → InstanceId
  51. implicit val platformConfig: PlatformConfig
  52. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  53. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  54. final val reset: Reset
    Definition Classes
    MultiIOModule
  55. val router: Router[Vec[T]]
  56. def suggestName(seed: ⇒ String): TCU.this.type
    Definition Classes
    HasId
  57. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  58. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  59. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  60. def toString(): String
    Definition Classes
    AnyRef → Any
  61. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  62. val validateInstructions: Boolean
  63. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  64. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  65. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  66. val weightsPort: Port[Vec[T]]
  67. val width: Int

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped