class Decoder extends Module
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- Decoder
- LegacyModule
- MultiIOModule
- RawModule
- BaseModule
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Visibility
- Public
- All
Instance Constructors
- new Decoder(arch: Architecture, options: TCUOptions = TCUOptions())(implicit platformConfig: PlatformConfig)
Value Members
-
final
def
!=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
-
def
IO[T <: Data](iodef: T): T
- Attributes
- protected
- Definition Classes
- BaseModule
- implicit val _arch: Architecture
-
def
_bindIoInPlace(iodef: Data): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
-
var
_closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
_compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
-
def
_compatIoPortBound(): Boolean
- Attributes
- protected
- Definition Classes
- LegacyModule
- val acc: DecoupledIO[AccumulatorMemControlWithSizeWithStride]
- def accBundle(instruction: Instruction, address: UInt, altAddress: UInt, read: Bool, write: Bool, accumulate: Bool, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
- val accDepth: Long
- val accHandler: SizeAndStrideHandler[AccumulatorMemControlWithSizeWithStride, AccumulatorMemControl]
- val accInGen: AccumulatorMemControlWithSizeWithStride
- val accOutGen: AccumulatorMemControl
- def accRead(address: UInt, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
- def accWrite(address: UInt, accumulate: Bool, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
- def allReady(ports: DecoupledIO[Data]*): Bool
- val arch: Architecture
- val array: DecoupledIO[SystolicArrayControlWithSize]
- def arrayBundle(load: Bool, zeroes: Bool, size: UInt): SystolicArrayControlWithSize
- val arrayHandler: SizeHandler[SystolicArrayControlWithSize, SystolicArrayControl]
- val arrayInGen: SystolicArrayControlWithSize
- val arrayOutGen: SystolicArrayControl
- val arrayWidth: Int
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
-
def
circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
-
final
val
clock: Clock
- Definition Classes
- MultiIOModule
-
def
clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native() @HotSpotIntrinsicCandidate()
-
val
compileOptions: CompileOptions
- Definition Classes
- RawModule
-
def
computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
- Definition Classes
- HasId
- val dataflow: DecoupledIO[DataFlowControlWithSize]
- def dataflowBundle(kind: UInt, size: UInt): DataFlowControlWithSize
- val defaultTimeout: Int
-
def
desiredName: String
- Definition Classes
- BaseModule
- val dram0: DecoupledIO[MemControlWithStride]
- val dram0AddressOffset: UInt
- val dram0CacheBehaviour: UInt
- val dram0Depth: Long
- val dram0Gen: MemControlWithStride
- val dram0Handler: StrideHandler[MemControlWithStride, MemControl]
- val dram1: DecoupledIO[MemControlWithStride]
- val dram1AddressOffset: UInt
- val dram1CacheBehaviour: UInt
- val dram1Depth: Long
- val dram1Gen: MemControlWithStride
- val dram1Handler: StrideHandler[MemControlWithStride, MemControl]
- def enqueue[T <: Data](port: DecoupledIO[T], value: T): Bool
- val enqueuer1: MultiEnqueue
- val enqueuer2: MultiEnqueue
- val enqueuer3: MultiEnqueue
- val enqueuer4: MultiEnqueue
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
def
equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
def
getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
-
def
getIds: Seq[HasId]
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
-
lazy val
getPorts: Seq[Port]
- Definition Classes
- RawModule
-
def
hasSeed: Boolean
- Definition Classes
- HasId
-
def
hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
-
def
instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val instruction: DecoupledIO[Instruction]
-
val
io: Bundle { ... /* 17 definitions in type refinement */ }
- Definition Classes
- Decoder → LegacyModule
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- implicit val layout: InstructionLayout
- val memDepth: Long
- val memPortA: DecoupledIO[MemControlWithStride]
- val memPortAGen: MemControlWithStride
- val memPortAHandler: SizeAndStrideHandler[MemControlWithStride, MemControl]
- val memPortB: DecoupledIO[MemControlWithStride]
- val memPortBGen: MemControlWithStride
- val memPortBHandler: SizeAndStrideHandler[MemControlWithStride, MemControl]
-
final
lazy val
name: String
- Definition Classes
- BaseModule
-
def
nameIds(rootClass: Class[_]): HashMap[HasId, String]
- Attributes
- protected
- Definition Classes
- BaseModule
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
-
var
override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- LegacyModule
-
var
override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- LegacyModule
-
def
parentModName: String
- Definition Classes
- HasId → InstanceId
-
def
parentPathName: String
- Definition Classes
- HasId → InstanceId
-
def
pathName: String
- Definition Classes
- HasId → InstanceId
- implicit val platformConfig: PlatformConfig
-
def
portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
-
def
portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val programCounter: UInt
- val registerWidth: Int
-
final
val
reset: Reset
- Definition Classes
- MultiIOModule
- val sampleInterval: UInt
- def setDefault[T <: Data](port: DecoupledIO[T]): Unit
- val status: Queue[WithLast[Instruction]]
-
def
suggestName(seed: ⇒ String): Decoder.this.type
- Definition Classes
- HasId
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
- val timeout: UInt
- val timer: UInt
-
final
def
toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
-
final
def
toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
-
def
toString(): String
- Definition Classes
- AnyRef → Any
-
final
def
toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val tracepoint: UInt
- val validateInstructions: Boolean
-
final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
-
final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... ) @native()
-
final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
Deprecated Value Members
-
def
finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws( classOf[java.lang.Throwable] ) @Deprecated
- Deprecated