c

tensil.tcu

Decoder

class Decoder extends Module

Linear Supertypes
LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, InstanceId, AnyRef, Any
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Inherited
  1. Decoder
  2. LegacyModule
  3. MultiIOModule
  4. RawModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new Decoder(arch: Architecture, options: TCUOptions = TCUOptions())(implicit platformConfig: PlatformConfig)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. implicit val _arch: Architecture
  6. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  7. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  8. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  9. def _compatIoPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  10. val acc: DecoupledIO[AccumulatorMemControlWithSizeWithStride]
  11. def accBundle(instruction: Instruction, address: UInt, altAddress: UInt, read: Bool, write: Bool, accumulate: Bool, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
  12. val accDepth: Long
  13. val accHandler: SizeAndStrideHandler[AccumulatorMemControlWithSizeWithStride, AccumulatorMemControl]
  14. val accInGen: AccumulatorMemControlWithSizeWithStride
  15. val accOutGen: AccumulatorMemControl
  16. def accRead(address: UInt, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
  17. def accWrite(address: UInt, accumulate: Bool, size: UInt, stride: UInt): AccumulatorMemControlWithSizeWithStride
  18. def allReady(ports: DecoupledIO[Data]*): Bool
  19. val arch: Architecture
  20. val array: DecoupledIO[SystolicArrayControlWithSize]
  21. def arrayBundle(load: Bool, zeroes: Bool, size: UInt): SystolicArrayControlWithSize
  22. val arrayHandler: SizeHandler[SystolicArrayControlWithSize, SystolicArrayControl]
  23. val arrayInGen: SystolicArrayControlWithSize
  24. val arrayOutGen: SystolicArrayControl
  25. val arrayWidth: Int
  26. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  27. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  28. final val clock: Clock
    Definition Classes
    MultiIOModule
  29. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  30. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  31. def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String]
    Definition Classes
    HasId
  32. val dataflow: DecoupledIO[DataFlowControlWithSize]
  33. def dataflowBundle(kind: UInt, size: UInt): DataFlowControlWithSize
  34. val defaultTimeout: Int
  35. def desiredName: String
    Definition Classes
    BaseModule
  36. val dram0: DecoupledIO[MemControlWithStride]
  37. val dram0AddressOffset: UInt
  38. val dram0CacheBehaviour: UInt
  39. val dram0Depth: Long
  40. val dram0Gen: MemControlWithStride
  41. val dram0Handler: StrideHandler[MemControlWithStride, MemControl]
  42. val dram1: DecoupledIO[MemControlWithStride]
  43. val dram1AddressOffset: UInt
  44. val dram1CacheBehaviour: UInt
  45. val dram1Depth: Long
  46. val dram1Gen: MemControlWithStride
  47. val dram1Handler: StrideHandler[MemControlWithStride, MemControl]
  48. def enqueue[T <: Data](port: DecoupledIO[T], value: T): Bool
  49. val enqueuer1: MultiEnqueue
  50. val enqueuer2: MultiEnqueue
  51. val enqueuer3: MultiEnqueue
  52. val enqueuer4: MultiEnqueue
  53. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  54. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  55. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  56. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  57. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  58. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  59. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
  60. def hasSeed: Boolean
    Definition Classes
    HasId
  61. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  62. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  63. val instruction: DecoupledIO[Instruction]
  64. val io: Bundle { ... /* 17 definitions in type refinement */ }
    Definition Classes
    Decoder → LegacyModule
  65. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  66. implicit val layout: InstructionLayout
  67. val memDepth: Long
  68. val memPortA: DecoupledIO[MemControlWithStride]
  69. val memPortAGen: MemControlWithStride
  70. val memPortAHandler: SizeAndStrideHandler[MemControlWithStride, MemControl]
  71. val memPortB: DecoupledIO[MemControlWithStride]
  72. val memPortBGen: MemControlWithStride
  73. val memPortBHandler: SizeAndStrideHandler[MemControlWithStride, MemControl]
  74. final lazy val name: String
    Definition Classes
    BaseModule
  75. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  76. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  77. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  78. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  79. var override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  80. var override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  81. def parentModName: String
    Definition Classes
    HasId → InstanceId
  82. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  83. def pathName: String
    Definition Classes
    HasId → InstanceId
  84. implicit val platformConfig: PlatformConfig
  85. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  86. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  87. val programCounter: UInt
  88. val registerWidth: Int
  89. final val reset: Reset
    Definition Classes
    MultiIOModule
  90. val sampleInterval: UInt
  91. def setDefault[T <: Data](port: DecoupledIO[T]): Unit
  92. val status: Queue[WithLast[Instruction]]
  93. def suggestName(seed: ⇒ String): Decoder.this.type
    Definition Classes
    HasId
  94. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  95. val timeout: UInt
  96. val timer: UInt
  97. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  98. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  99. def toString(): String
    Definition Classes
    AnyRef → Any
  100. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  101. val tracepoint: UInt
  102. val validateInstructions: Boolean
  103. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  104. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  105. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped